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uClamp3324P
PROTECTION PRODUCTS
Applications Information
Device Connection Options
Figure 1 - Circuit Diagram
The μClamp3324P is designed to protect four lines. It
will present a high impedance to the protected line up
1
8
2
7
3
6
4
5
to 3.3 volts. It will “turn on” when the line voltage
exceeds 3.5 volts. The device is unidirectional and
may be used on lines where the signal polarity is above
ground.
Flow Thru Layout
The μClamp3324P is designed for ease of PCB layout
by allowing the traces to enter one side of the device
and exit the other side. Figure 2 shows the
recommended way to design the PCB board traces in
order to use the flow through layout. The solid line
represents the PCB trace. Note that the PCB traces
enter at the input pin and exit from the opposite pin.
(pin 1 to pin 8, pin 2 to pin 9, pin 3 to pin 6, pin 4 to
pin 5). For example, line 1 enters at pin 1 and exits at
Pin 8. The bottom tab is connected to ground. This
GND
Figure 2 - Layout Example
connection should be made directly to a ground plane
on the board for best results. The path length is kept
as short as possible to minimize parasitic inductance.
EPD TVS Characteristics
These devices are constructed using Semtech’s
proprietary EPD technology. The structure of the EPD
TVS is vastly different from the traditional pn-junction
devices. At voltages below 5V, high leakage current
In 1
In 2
In 3
In 4
Out 1
Out 2
Out 3
Out 4
and junction capacitance render conventional ava-
lanche technology impractical for most applications.
However, by utilizing the EPD technology, these devices
can effectively operate at 3.3V while maintaining
excellent electrical characteristics.
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in tradi-
tional silicon-avalanche TVS diodes. The EPD mecha-
nism is achieved by engineering the center region of
Figure 3 - EPD TVS IV Characteristic Curve
I PP
I SB
the device such that the reverse biased junction does
not avalanche, but will “punch-through” to a conduct-
V F
I PT
I R
ing state. This structure results in a device with supe-
rior DC electrical parameters at low voltages while
maintaining the capability to absorb high transient
currents.
I F
V RWM
V SB V PT V C
? 2005 Semtech Corp.
4
www.semtech.com
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